Regviz

Silicon Labs /Series1 /EFR32FG14P /EFR32FG14P231F128GM48 /WDOG1 /CTRL

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Interpret as CTRL

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31282724232019161512118743000000000000000000000000000000000000000000 (EN)EN0 (DEBUGRUN)DEBUGRUN0 (EM2RUN)EM2RUN0 (EM3RUN)EM3RUN0 (LOCK)LOCK0 (EM4BLOCK)EM4BLOCK0 (SWOSCBLOCK)SWOSCBLOCK0PERSEL0 (ULFRCO)CLKSEL0WARNSEL0WINSEL0 (CLRSRC)CLRSRC0 (WDOGRSTDIS)WDOGRSTDIS

CLKSEL=ULFRCO

Description

Control Register

Fields

EN

Watchdog Timer Enable
DEBUGRUN

Debug Mode Run Enable
EM2RUN

Energy Mode 2 Run Enable
EM3RUN

Energy Mode 3 Run Enable
LOCK

Configuration Lock
EM4BLOCK

Energy Mode 4 Block
SWOSCBLOCK

Software Oscillator Disable Block
PERSEL

Watchdog Timeout Period Select
CLKSEL

Watchdog Clock Select

0 (ULFRCO): ULFRCO

1 (LFRCO): LFRCO

2 (LFXO): LFXO

3 (HFCORECLK): HFCORECLK
WARNSEL

Watchdog Timeout Period Select
WINSEL

Watchdog Illegal Window Select
CLRSRC

Watchdog Clear Source
WDOGRSTDIS

Watchdog Reset Disable

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data